The invention generally relates to mobile communication devices such as cellular telephones and in particular to flash memory and static random access memory (SRAM) for use therein.
A flash memory is a type of non-volatile memory that retains stored information even after power is disconnected. This is in contrast with volatile memory devices, such as SRAM or dynamic RAM (DRAM), which lose data stored therein once power has been disconnected. In addition to being non-volatile, flash memory is electrically erasable and reprogrammable within the system in which it is incorporated. This is in contrast with other non-volatile memory devices, such as erasable, programmable read-only memory (EPROM) which typically requires special voltages for reprogramming and, hence, is typically only reprogrammable by a manufacturer or service specialist.
Accordingly, flash memory is advantageously employed within devices requiring non-volatile memory that can be selectively erased and reprogrammed. In particular, flash memory is well-suited for use in desktop personal computers, laptop computers, video game cartridges, digital voice recorders, personal digital assistants (PDAs), and cellular telephones (or other mobile stations of wireless communication systems). Typically, within such systems, the flash memory is configured as a single flash macro, which can either be written to or read from, but not both, at any given time. For most devices this is sufficient. For example, within most devices containing flash memory, any data to be stored within the flash memory is stored within volatile memory until the device is to be shut off, then the flash memory is reprogrammed with the data during a shut-down operation. As such, it is unlikely that the device will ever need to both read from and write to the flash memory at the same time. As one example, a PC or laptop computer may store changes to a basic input/output system (BIOS) within a DRAM memory until the computer is to be shut down, then the changes to the BIOS are transferred to flash memory.
Problems, however, arise when attempting to implement flash memory within a cellular telephone which may require many more frequent read operations and write operations to the flash memory. Cellular telephones consume a considerable amount of power during use and, to be commercially desirable, the cellular telephone must be able to operate effectively for long periods of time between recharging. As a result, cellular telephones are typically configured to shut down power to internal components as often as possible. Within CDMA cellular telephones, for example, many components are powered down between each successive paging slot of the CDMA system. (The paging slots occur 30 milliseconds apart.) Accordingly, it is not feasible to accumulate pending write operations within a non-volatile memory until a single final power shut-down operation. Rather, data to be written to the flash memory may need to be written promptly prior to each successive temporary power shut-down. Moreover, the need to frequently reprogram the flash memory is typically much greater within a cellular telephone, particularly within a cellular smart phone, i.e., a cellular telephone configured with a PDA to thereby provide both cellular telephony functions and PDA functions. Insofar as computers are concerned, a flash memory may only need to be reprogrammed in the event there are changes to the BIOS or other configuration parameters of the system. With a cellular smart phone, the flash memory may need to be frequently reprogrammed to record new telephone numbers, addresses, calendar dates, meeting dates and the like. For smart phones configured to record voice memos, the flash memory may need to be reprogrammed whenever the uses of the telephone records a voice memo. Accordingly, reading and writing operations may need to be performed much more frequently in connection with cellular telephones and the conventional flash memory arrangement, whereby reading from and writing to the flash memory cannot be performed simultaneously, may be inadequate.
Moreover, within cellular telephone applications, the flash memory may need to be accessed much more quickly than is required in other applications. This is particularly true if the data to be retrieved from the flash memory is required for use in connection with any real time functions of the cellular telephone, such as voice telephone calls. For such functions, any delay necessitated by having to wait for a previous write operation to be completed before reading from the flash memory may be significant.
Furthermore, even if a read operation need not be delayed pending completion of a write operation, read times within conventional flash memories can be fairly slow. Flash memories become degraded with use such that the read time for particular flash cells that have been frequently rewritten become slow in comparison with flash cells that have not been frequently rewritten. Hence, after a device containing flash memory has been used for some time, some of the flash cells have slower read times than others. To account for possible degradation, devices containing flash cells typically set an internal flash memory read time to be relatively slow. In this regard, a bus system connected to the flash memory for retrieving data from the flash memory is pre-programmed with a number of wait states sufficient to account for the potentially slow access times of cells that may become degraded. In other words, the bus system is pre-programmed to accommodate the worst case scenario insofar as flash memory access time is concerned. As a result, all read accesses are relatively slow, even from flash memory locations which have not yet been degraded. In many devices, the slow read time is not problematic. However, in connection in with cellular telephones, it is much more important to minimize the time required for each access from flash memory, particularly while the cellular telephone is engaged in real time functions. Accordingly, it would be highly desirable to provide an improve flash memory system, particularly for use within cellular telephones or similar devices which overcome the disadvantages set forth above. It is to this end that aspects of the present invention are directed.
Typically, within cellular telephones, a flash memory is used in conjunction with an SRAM, wherein the flash memory provides for non-volatile storage and the SRAM provides for volatile storage. Typically, the flash memory and SRAM devices are separate devices from one another and are also mounted separately from a primary ASIC of the cellular telephone which includes the microprocessor and the various peripheral components for handling cellular telephony functions. In such implementations, because of the flash and the SRAM memories are separate from the ASIC, the time required to access the flash memory and the SRAM can be relatively slow, thus, hindering overall system performance. Accordingly, it is also desirable to provide an improved system architecture for use within cellular telephones having flash memory, SRAM and a central ASIC which permits expedited access to the flash and SRAM memories and it is to this end that other aspects of the invention are directed.
Also, because the flash memory of the cellular telephone may need to be accessed frequently, there is a risk that portions of data stored within the flash memory may be inadvertently overwritten. This is particularly true in state-of-the-art cellular telephones which may include the numerous hardware components each capable of reprogramming portions of the flash memory. This problem is exacerbated by the fact that a software for use within cellular telephones typically must be developed and brought to market very quickly to accommodate the fast-changing marketplace. As a result, there is a fairly significant risk that software may inadvertently cause portions of data within the flash memory to be re-written or erased. This can be a serious problem if the portion of flash memory inadvertently erased stored important telephone numbers, such as police numbers, fire department numbers and the like or stored important software programs, such as boot loaders and the like required for operation of the telephone. Accordingly, it is highly desirable to provide an improved flash memory system which minimizes the risk of inadvertent erasure of portions of the flash memory and still further aspects of the invention are directed to this end.
In accordance with a first aspect of the invention, a flash memory system is provided with a read while writing means for writing to one of the flash macros while simultaneously reading from another of the flash macros. In one specific example, wherein the flash memory system is connected to a microprocessor, the read while writing means includes means for writing signals received from the microprocessor to a selected one of the flash macros and means, responsive to receipt of a read command from the microprocessor directed to the selected flash macro, for suspending operation of the microprocessor until the means for writing has completed its operation, then performing the read command.
Thus, the flash memory cells are divided into a set of flash macros which can be independently accessed. A write operation can be performed to one of the flash macros while a read operation is performed within another of the flash macros. This improves the overall system response time, in part because read operations need not be deferred until a write operation is completed. Indeed, since flash memory write operations typically take much longer than flash memory read operations, numerous read operations may be performed in parallel during a single flash memory write operation.
In accordance with a second aspect of the invention, a flash memory system is provided with programmable wait states. In an exemplary embodiment, flash memory cells are again arranged as a set of flash macros. A flash memory bus interconnects the flash macros and a flash memory controller. The flash memory controller includes a wait state register unit for storing a programmable number of wait states associated with the flash macros, with one programmable number of wait states per flash macro. The flash memory controller also includes a flash macro access unit for accessing a selected flash macro. Flash macro access unit accesses the selected flash macro using the flash memory bus program with the number of wait states associated with the selected flash macro. With this arrangement, portions of the flash memory which are frequently reprogrammed, and hence subject to degradation, can be accessed using a greater number of wait states than other portions of the flash memory. As a result, portions of the flash memory which are not frequently reprogrammed can be accessed much more quickly than within systems wherein all the read operations to the flash memory are delayed by some number of wait states to accommodate a worse case memory access time corresponding to a worse case amount of degradation.
In accordance with a third aspect of the invention, a flash memory system is provided with password protection. In an exemplary embodiment, the flash memory system includes flash memory cells arranged as a set of flash macros along with a flash memory controller having means for storing a separate password associated with each flash macro and the means, responsive to receipt of a valid password from a selected one of the flash macros, for enabling programming for erasing of flash cells of the selected flash macro while simultaneously preventing programming for erasing of all other flash cells. With this configuration, the risk of inadvertent erasure of the portions of the flash memory is greatly minimized. A valid password is acquired before an erasure operation can be performed. Hence, inadvertent erase operations resulting from software bugs and the like are greatly reduced. Moreover, by providing different passwords for different portions of the flash memory, individual computer programs or individual peripheral hardware components can be restricted to only erasing particular portions of the flash memory. As a result, the risks of inadvertent erasure or reprogramming of large portions of the flash memory is greatly reduced. In a specific implementation, a portion of the flash memory stores a boot loader for use in booting a system in which the flash memory resides. A separate password associated with the boot loader is provided to further minimize the risk of accidental reprogramming of the boot loader.
In accordance with a fourth aspect of the invention, a flash memory system is provided with a programmable memory map. Flash memory system includes flash memory cells and a flash memory controller provided with means for partitioning the flash memory cells into high and low memory locations. The flash memory cells store a boot loader beginning at a lowest memory address of the flash memory space. The means for partitioning includes the means for swapping the high and low memory locations after operations performed by the boot loader have been completed. With this arrangement, the boot loader, which is typically only accessed during an initial power-up operation, is swapped into high memory such that other data and programs which may need to be accessed more frequently can be stored within low memory where they can be accessed more expediently.
Other objects, features and advantages of the invention will be apparent from the descriptions which follow in conjunction with the attached drawings. Method and apparatus embodiments of the invention are provided.